Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops

Digital phase-locked loops based on bang-bang phase detectors are attractive candidates for low-jitter clock-frequency multiplication. Unfortunately, the coarse quantization of phase error makes these systems prone to the generation of limit cycles appearing as unwanted spurs in the spectrum. The random noise contributed by building blocks and acting as dithering signal can eliminate those spurs. The quantitative analysis of those phenomena becomes more involved when a DCO with relaxed intrinsic resolution, such as a ΔΣ-DCO is employed, and when practical spectra of random noise sources are considered. In this work, the expression of jitter is calculated in closed-form taking into account the quantization, introduced by both phase detector and DCO, and the phase noise of DCO, with both 1/f^2 and 1/^3 components. Combining these results, a closed-form expression of the total output jitter as a function of loop parameters and noise sources is developed which suggests a minimum-jitter design strategy. The proposed analysis and optimization are validated both numerically and experimentally on a 320-MHz digital bang-bang PLL fabricated in a 65-nm CMOS process

Low Power RF Digital PLLs with Direct Carrier Modulation

The book offers unique insight into the modern world of wireless communication that included 5G generation, implementation in Internet of Things (IoT), and emerging biomedical applications. To meet different design requirements, gaining perspective on systems is important. Written by international experts in industry and academia, the intended audience is practicing engineers with some electronics background. It explains how wireless electronic circuit receive and transmit RF signals and how they play an important role in everyday life applications (mobile devices, Internet, and Bluetooth). The text further explains how modern RF wireless systems are built and used in practical systems

Nonlinearity cancellation in digital PLLs (Invited paper)

One decade after their introduction into wireless applications, digital fractional-N phase-locked loops are becoming a competitive solution for products. Their ultimate level of spurs is often bounded by the resolution and the linearity of the time-to-digital converter. Although methods for mitigating its nonlinearity have been proven effective in lowering spurs, they typically increase the level of random noise. By contrast, digital-PLL architectures based on digital-to-time converters enable nonlinearity cancellation and spur reduction with no penalty on noise level, while reducing design complexity and power consumption

Analysis and Characterization of the Effects of Clock Jitter in A/D Converters for Subsampling

This paper investigates nature and effects of jitter on the clock edge that triggers the sample/hold used in direct-sampling and IF-sampling receiver architectures. The impact of the aperture uncertainty is theoretically discussed, simulated, and measured in the case of the high-frequency front-end of a 16-bit 65 MS/s analog–digital converter. Both characterizations of the phenomenon are considered: in the frequency domain [single-sideband to carrier ratio (SSCR), or phase noise] and in the time domain (aperture jitter)

Oscillatore LC

ll brevetto riguarda un nuovo array di oscillatori LC accoppiati. La novità risiede nella modalità utilizzata per accoppiare le varie celle. Nella topologia classica si utilizza in ogni cella un transconduttore per bilanciare le perdite del tank e uno per accoppiare l'oscillatore al resto della rete. Nella presente soluzione invece, è presente un solo transconduttore per cella, che contemporaneamente bilancia le perdite e concede l'accoppiamento. Il principale vantaggio della soluzione proposta è la riduzione della up-conversion del rumore flicker in rumore di fase 1/f^3, effetto molto limitante nelle realizzazioni CMOS

A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity

A novel technique for automatic digital estimation and foreground correction of static distortion in Analog-to-Digital Converters (ADCs) is presented. The system exploits numerical Phase-Locked Loops (NPLLs) to autonomously generate a distortion-less replica of the input signal and to detect the spurs due to the ADC non linearity. The information is then fed to filters adaptively estimating, via Least Mean Squares (LMS) algorithms, a polynomial correction from the orthogonal inverse series. The solution is fully digital, does not require post-processing and can be expanded to cancel out the static distortion up to an arbitrary order. Performance is tested by simulations on a 12 bit ADC operating at 200MHz with a native Signal-to-Noise and Distortion Ratio (SINAD) of 54.9dB. Polynomial compensation up to the third order is generated in 1ms, improving the SINAD by 12dB and adding 2 effective bits of resolution and more than doubling the input range of the converter

A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications

A 5-GHz, fully monolithic voltage-controlled oscillator (VCO) for Bluetooth wireless transceivers is demonstrated in a 0.25 μm CMOS technology using accumulation mode varactors and spiral inductors. An 18% tuning range was measured for only 2.5 V tuning-voltage variation. The phase noise was -94 dBc/Hz at 100 kHz frequency offset with 40 kHz 1/f3 corner frequency. These low values are limited by the up-conversion of flicker noise due to varactor amplitude-to-frequency conversion and to the modulation of the varactor bias point. This explanation is verified by simulations and measurements. The circuit draws 5.5 mA from a 2.5 V power suppl